|Port Type||Name||Width (bits)||Description|
This page provides detailed information about the SystemC TLM2 Fast Processor Model of the Renesas V850E1F core.
Processor IP owner is Renesas (formerly NEC).
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
Model downloadable (needs registration and to be logged in) in package v850.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.
Model Variant name: V850E1F
V850 Family Processor Model.
Open Source Apache 2.0
The following Debug Registers are non-functional DIR, BPC0, BPC1, ASID BPAV0, BPAV1, BPAM0, BPAM1 BPDV0, BPDV1, BPDM0, BPDM1
Models have been extensively tested by Imperas, In addition Verification suites have been supplied by Renesas for Feature Set validation
All v850e1 single precision FPU Instructions are supported.
All v850e1 Instructions are supported.
All Program and System Registers are supported.
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant V850E1F is available OVP_Model_Specific_Information_v850_V850E1F.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: renesas.ovpworld.org/processor/v850/1.0
Processor Endian-ness: This model is little endian.
Processor ELF Code: The ELF code for this model is: 0x57
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.
The V850E1F SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_v850_V850E1F.pdf.
Information on the V850E1F OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library
http://www.ovpworld.org: Simulation Control of Platforms and Modules User Guide
http://www.ovpworld.org: Creating & Using Platforms and Models in C++ with OP API
http://www.ovpworld.org: riscvOVPsim. A complete RISC-V ISS for bare-metal software development and Specification Compliance Test Development
http://www.ovpworld.org: RISC-V Bare Metal Demos Video Presentation
Currently available Fast Processor Model Families.